1. Field of the Invention
The present invention relates to a semiconductor memory device composed of ferroelectric memories.
2. Description of Related Art
Memory cells constituting a semiconductor memory device (ferroelectric memory) using polarization of ferroelectrics are well known to be of a 2T2C type and 1T1C type, as described in Reference 1 (“Low-power High-speed LSI Circuits & Technology”, Realize Ltd., pp. 231-250) and Reference 2 (“All About Non-Erasable IC Memory-FRAM”, K. K. Kogyo Chosakai, pp. 29-37). The 2T2C-type memory cell is composed of two transistors and two ferroelectric capacitors, whereas a 1T1C-type memory cell is composed of one transistor and one capacitor.
The polarization state of a ferroelectric capacitor of the above-described memory cell is usually determined by a hysteresis curve, as disclosed in Reference 1. FIG. 8 shows such a hysteresis curve 18. In the figure, the polarization P (μC/cm2) is plotted against the ordinate, and the voltage V (V) is plotted against the abscissa.
The hysteresis curve 18 shown in FIG. 8 intersects with the ordinate in A point and B point when the voltage is 0. The A point and B point represent two residual polarization quantities of the ferroelectric capacitor. Thus, depending on the two residual polarization states shown in FIG. 8, a ferroelectric capacitor holds “L” (low-level state, that is, a state without voltage, or a state with a low voltage) data or “H” (high-level state, that is, a state with a voltage) data. When the residual polarization in the ferroelectric capacitor is represented by A point, “H” data are held, and when the residual polarization is represented by B point, the “L” data are held.
The above-described memory cell is connected to a sense amplifier with a bit line. As disclosed in Reference 1 and Reference 2, the reading operation of the ferroelectric memory composed of the above-described memory cells is the same as that of DRAM (Dynamic RAM (Random Access Memory)). Therefore, the bit line voltage generated by voltage division between the ferroelectric capacitor and bit line capacity Cb is detected by the sense amplifier. Further, according to Reference 1, the bit line voltage is determined by the shape of the hysteresis curve of ferroelectric capacitor and the bit line capacity Cb.
Referring to FIG. 8, a load line 10 and a load line 12 corresponding to the two residual polarization states of ferroelectric capacitor represented by A point and B point are shown in addition to the hysteresis curve 18. The slope of those load curve 10 and load curve 12 is the bit line capacity Cb. Further, in the hysteresis curve 18, the section between the A point and E point is the region of the non-inverted response of the ferroelectric capacitor, and the section between the B point and E point is the region of the reversed response of the ferroelectric capacitor. The read-out bit line voltage V0 and bit line voltage V1 in the two memory states of ferroelectric capacitor is found from intersection point C of the load line 10 and section between the A point and E point in the hysteresis line 18, from intersection point D of the load line 12 and the section between the B point and E point in the hysteresis line 18, and from the E point. The difference ΔV between those bit line voltage V0 and bit voltage V1 should be no less than the discrimination sensitivity of sense amplifier.
The read operation of the above-described ferroelectric memory is a destructive read, similarly to DRAM. If the polarization of a ferroelectric capacitor is repeatedly reversed in the read operation and write operation of the ferroelectric capacitor, the polarization of the capacitor decreases. This effect is inherent to ferroelectric memory and is usually called a fatigue (fatigue characteristic). In FIG. 8, the hysteresis curve 20 of a ferroelectric capacitor degraded due to fatigue is shown by a dotted line. In this case, a bit line voltage V′0 and a bit line voltage V′1 can be found from intersection point C′ of the load line 14 and hysteresis curve 20, from intersection point D′of the load line 16 and hysteresis line 20, and from the E point by the same procedure as described above. Here, the slope of load curve 14 and load curve 16 is also the bit line capacity Cb. The difference ΔV′ between the bit line voltage V′0 and bit line voltage V′1 in the ferroelectric capacitor degraded by fatigue decreases below the above-described difference ΔV between the bit line voltage V0 and bit line voltage V1 and becomes less than the discrimination sensitivity of sense amplifier. At this time, the ferroelectric memory comprising the degraded ferroelectric capacitor is considered to be degraded.
Evaluation of the above-mentioned fatigue is typically conducted by reliability testing the device comprising the ferroelectric memory. Reliability testing that has been conventionally conducted with respect to fatigue is disclosed in Published Reference Material 1 (“Assurance of Fujitsu FRAM Quality and Reliability”, 2002, Fujitsu Home Page (http://edevice.fujitsu.com/fj/CATAROG/AD00/00-00015/1-7.html)).
A screening test is conducted as a reliability test relating to fatigue. The screening test is a test conducted to detect defective memory cells in a device. The screening test, as disclosed in Published Reference Material 1, is conducted by applying fatigue stresses by repeating the prescribed number of read and write cycles in the ferroelectric memory constituting the device and then checking whether the ferroelectric memory operates normally. This test is called a cycling test. When no defective memory cells that were degraded by fatigue of ferroelectric capacitors have been detected by the cycling test consisting of the prescribed number of cycles, this number of cycles is considered an assurance number of cycles.
However, the production devices are generally not subjected to the cycling test consisting of the assurance number of cycles in the screening test. For example, when the assurance number of cycles T is 1.0×1012, the production device is subjected to a test consisting of only 1×1010 cycles. If no defective memory cell has been detected in the cycling test consisting of 1×1010 cycles, a prediction is made that no defective memory cell will likewise be detected if the device is subjected to T=1.0×1012 cycles of cycling test. This prediction is based on data obtained in the cycling tests consisting of 1.0×1012 cycles that were conducted on non-production devices and TEG (wafers or chips carrying circuits or elements for evaluation which are produced when a new production process is developed and standardized or when a net circuit design is created). Thus, with the above-described screening test, a spread of assurance numbers of cycles T between the devices is not taken into account and all of the devices that passed the 1.0×1010 cycling test are assumed to have an assurance number of cycles of 1.0×1012. For this reason, problems were associated with fatigue-related reliability of devices having an assurance number of cycles T determined by the above-described cycling test.